The present invention relates to a method and/or architecture for implementing phase lock loops (PLLs) generally and, more particularly, to a method and/or architecture for implementing PLL charge pump circuits.
PLLs are often considered to be clock multipliers. For example, an input clock of 10 Mhz can be multiplied by a PLL to yield an output frequency of 1000 Mhz. Ideally, the clock multiplication would result in an output clock that is in perfect phase alignment with the input clock.
Referring to FIG. 1, a conventional PLL architecture 10 is shown. The PLL 10 includes a phase frequency detector (PFD) 12, a charge pump 14, a filter 16, a voltage controlled oscillator (VCO) 18, and a divider 20. The PFD 12 sends the charge pump 14 information about the frequency and phase of the reference signal REF relative to the feedback clock FB. The charge pump 14 pumps up or down the frequency and presents a signal to the filter 16. The filter 16 integrates the filter information into a voltage. The VCO 18 converts the voltage information into the frequency CLK_OUT. The divider 20 divides down the higher speed frequency for a comparison by the PFD 12. A divider 22 divides the input frequency CLK_IN before being presented to the PFD 12 as the reference frequency REF.
Referring to FIG. 2, a detailed block diagram of the pump 14 is shown. The signals PD, PDN, PUN and PU control a number of switches to generate the negative filter input signal FILTERxe2x88x92. The signals PD, PDN, PUN and PU also control generation of the positive filter input signal FILTER+. Generation of the signals FILTERxe2x88x92 and FILTER+ is controlled by the common mode adjust circuit 30.
RF radio receivers lock to new frequency channels (i.e., frequency hopping). Between locks, the PLL 10 is powered down. Once the PLL 10 is re-activated, the PLL circuit 10 can generate faulty pump signals. The PLL 10 can head in the wrong direction by mistakenly charging the input filter nodes FILTERxe2x88x92 and FILTER+. The configuration of the pump element 14 is important, since the lock time specification is short. By tri-stating the pump 14 prior to powering down processing invalid signals can be avoided. A similar sequence is used when powering up.
Referring to FIG. 3, the PFD 12 can be reset internally via the reset signal RESET. However, the PFD 12 is reset too early in the feedback path. Therefore, the charge pump 14 can arrive in a wrong state while biasing down (or up). While in the wrong state, the pump 14 could wrongly charge up (or down) the input filter nodes FILTERxe2x88x92 or FILTER+ presented to the filter 16.
Referring to FIG. 4, a multiplexer 24 can be added to the circuit 10. Alternatively, the multiplexer 24 could be replaced by a number of gates. The multiplexer (or gates) 24 is included to disable the output of the PFD 12 presented to the pump 14. The multiplexer 24 is also implemented too early in the feedback path. The charge pump 14 can still can arrive in a wrong state while biasing down (or up). While in the wrong state, the pump 14 could wrongly charge up (or down) the input filter nodes FILTERxe2x88x92 or FILTER+. Additionally, the multiplexer 24 adds load and uses extra current.
Another conventional approach is to power down the pump 14 until the PLL 10 is functional. However, the pump 14 can still arrive in the wrong state while biasing down (or up). During the wrong state, the pump 14 could wrongly charge up (or down) the input filter nodes FILTERxe2x88x92 or FILTER+.
It is generally desirable to provide a method and/or architecture for implementing PLL charge pump circuits that allows the PLL signal to be gated as close as possible to the output.
The present invention concerns an apparatus comprising a phase lock loop (PLL) and a charge pump. The PLL may be configured to generate an output signal in response to an input signal. The charge pump may be configured within the PLL and be configured to (i) pump-up the input signal, (ii) pump-down the input signal or (iii) enter tri-state in response to a control signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing PLL charge pump circuits that may (i) implement local transistors for current steering at a source of the main differential pair of a charge pump, (ii) implement local transistors for current steering at a source of the biasing transistors of a charge pump, (iii) implement local transistors operating at full CMOS levels to tri-state (or activate) a charge pump, (iv) allow current steering into the unused node (e.g., dump node) allowing drain to source voltage matching, (v) implement transistors for tri-stating that may be used as spare transistors in normal operation, (vi) allow a sequence of power down events, (vii) enable tri-stating prior to pump power down, (viii) allow a sequence of power up events, (ix) enable tri-stating prior to power up, and/or (x) provide a differential charge pump with tri-state capabilities implemented with minimum number of transistors (e.g., only 4 transistor may be used to tri-state).